ETD

• CRYSTALS-Dilithium
• CRYSTALS-Kyber
• fast models
• FPGA
• hardware accelerator
• lattice-based cryptography
• Number Theoretic Transform
• post-quantum cryptography
• SystemC TLM
• Verilator

Post-quantum cryptography is one of the most important fields of modern cryptographic research, as the development of quantum computing threatens the security of many public-key cryptographic schemes currently in use. In this context, the algorithms CRYSTALS-Kyber and CRYSTALS-Dilithium, later recognised by the NIST as standards ML-KEM and ML-DSA, are two of the main lattice-based primitives intended for future cryptographic use.

While these algorithms are intended for software implementation, much of their computational effort involves polynomial arithmetic, matrix-vector multiplication, and the Number Theoretic Transform. This drives research into specialised hardware accelerators to reduce the processing burden on the main processor and improve efficiency. However, designing and validating these accelerators requires precise yet adaptable simulation environments. Although traditional RTL simulation provides detailed insight into hardware performance, it may be less suitable for extensive testing, automated benchmarking, and integration with software components.

This thesis examines the development and deployment of a rapid Verilator-based model of the CRYPHTOR hardware accelerator. This RTL IP is designed to accelerate polynomial calculations in Kyber and Dilithium. Starting from the RTL description of the accelerator, Verilator generates an executable C++ model. A software harness is built around this model to handle clock and reset signals, perform AXI-Lite register accesses, simulate external memory, manage DMA transfers, initiate hardware processes, and collect results.

The developed model is validated by comparing the accelerator output with the software golden model across the supported operations. The simulation environment provides dedicated facilities for functional validation, benchmarking, and stress testing, and also allows measurements to be collected at the cycle level and experimental reports to be generated in CSV and Markdown formats. The work also contrasts traditional RTL simulation with the Verilator-based method, emphasising their complementary roles: detailed signal-level debugging and observability versus automation, programmability, and integration with C++ code.

Finally, the thesis analyses the integration of the fast model with PQClean, evaluating the use of the simulated accelerator within a more realistic cryptographic workflow. This integration highlights how the model could be used not only to validate the RTL in isolation, but also as part of the hardware/software co-design process, in which some polynomial primitives are delegated to the accelerator whilst the rest of the algorithm is executed in software.