Sistema ETD

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Tesi etd-04182011-114349


Tipo di tesi
Tesi di dottorato di ricerca
Autore
ANTICHI, GIANNI
URN
etd-04182011-114349
Titolo
Fast Packet Processing on High Performance Architectures
Settore scientifico disciplinare
ING-INF/03
Corso di studi
INGEGNERIA DELL'INFORMAZIONE
Commissione
tutor Prof. Russo, Franco
tutor Prof. Giordano, Stefano
Parole chiave
  • Network Processors
  • High Performance
  • Hash Functions
  • FPGA
  • Next Generation Networks
  • Deep Packet Inspection
  • Packet Classification
Data inizio appello
30/05/2011;
Disponibilità
completa
Riassunto analitico
The rapid growth of Internet and the fast emergence of new network applications have brought great challenges and complex issues in deploying high-speed and QoS guaranteed IP network. For this reason packet classi cation and network intrusion detection have assumed a key role in modern communication networks in order to provide Qos and security. In this thesis we describe a number of the most advanced solutions to these tasks. We introduce NetFPGA and Network Processors as reference platforms both for the design and the implementation of the solutions and
algorithms described in this thesis. The rise in links capacity reduces the time available to network devices for packet processing. For this reason, we show different solutions which, either by heuristic and randomization or by smart construction of state machine, allow IP lookup, packet classification and deep packet inspection to be fast in real devices based on high speed platforms such as NetFPGA or Network Processors.
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