Tipo di tesi
Tesi di laurea magistrale
Titolo
Worst-Case analysis of a DRAM Controller with FR-FCFS policy
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
COMPUTER ENGINEERING
Riassunto (Italiano)
Analysis of an upper bound on the delay experienced by the access requests targeting the main memory. The worst-case delay is also a starting point to build more useful tools that help with the evaluation of memory performance: the main purpose of this work is, in fact, to derive a minimum service curve for a DRAM whose controller applies a FR-FCFS policy in servicing queued requests. Starting from basic propositions and their proofs, the worst-case is evaluated algorithmically: a particular sequence of events is built that leads to the maximum delay.
