• calibration
• DDR
• dynamic power consumption
• early power estimates
• modelling methodology
• physical memory interface
• power modelling
• simulation validation
• stand-by power consumption

This thesis presents a power modelling framework for processor-to-memory interfaces, addressing the growing demand for accurate power estimation in complex electronic systems. A modular and scalable approach is developed, focusing on simplifying the estimation process while maintaining accuracy and adaptability. The model integrates analytical and empirical techniques to predict both static and dynamic power consumption, validated against simulation data across various configurations. Results demonstrate the model’s robustness, showing it to be effective in supporting early-stage design decisions in high-performance, energy-efficient circuit design. This work contributes to advancements in power-aware design, with implications for multiple applications in next-generation computing architectures.