• access
• accesso
• cache
• esecuzione
• memoria
• memory
• networkcalculus
• predicibile
• predictable
• wcet
• worstcase

This work aims to analyse the most commonly cache memory structures in order to find an analytical model able to predict the worst-case access time, under specific hypothesis. The proposed model is made by using the Network Calculus theory, where the cache hardware block and the memory accesses are treated as a normal network router and packets, respectively. Since the memory access ordering is application dependent, the framework called AMBA traffic profile has been used, which defines access patterns through a set of parameters (i.e., address base, address range). A cache simulator have been developed, which provides, given a specific traffic profile, the cache performances. Through the information given by the simulator and the cache memory model, an estimation of the worst-case access time is computed. Different classes of applications, defined by its AMBA profiles, have been studied.