ETD

• StrongARM
• TRNG

This thesis presents the design, modeling, and post-layout characterization of an integrated True Random Number Generator (TRNG) in TSMC 65 nm Low- Power CMOS technology. The research was carried out in collaboration with Quantavis within the EntropIC project, funded by the European Innovation Council (EIC) under the Horizon Europe programme. The project aims to develop a comprehensive, end-to-end anti-counterfeiting and identity management platform based on proprietary mixed-signal smart tags for luxury goods, pharmaceuticals, and distributed Internet of Things (IoT) devices. In the envisioned on-chip security architecture, the TRNG operates alongside a Physical Unclonable Function (PUF), supplying the fresh, unpredictable physical randomness required for cryptographic nonce generation and secure authentication protocols.
The entropy source employs four parallel Self-Compensating StrongARM (SC- SA) cells combined via an XOR tree, meeting the strict power and area constraints of the passive application while guaranteeing the generation of 96-bit nonces with full entropy through AES-256 CBC-MAC cryptographic conditioning. To drastically reduce start-up latency and silicon footprint while preserving raw min-entropy requirements, an innovative dual-step (coarse + fine) calibration mechanism was combined with the downsizing of the nMOSCAP compensation capacitors via behavioral step-size optimization, minimizing analog cell area and cutting the calibration transient by 77.9% to reach the thermal-noise-dominated metastable regime in only 19 clock cycles.
Validation was conducted using a hybrid flow combining post-layout parasitic extraction (PEX) in Cadence Virtuoso with high-throughput behavioral modeling to execute the NIST SP 800-90B test suite. The implemented TRNG occupies a compact area of 1408 µm2, exhibits an energy consumption of only 90 fJ/bit, and produces bitstreams complying with the project min-entropy specifications (Hmin ≥0.75 bit/bit), with over 99.45% of simulated complete TRNG instances exceeding the minimum entropy threshold across the wide temperature range (from −40◦C to +120◦C) and under worst-case process corners. The system is completed by the logic synthesis of a dedicated digital controller for managing the start-up protocol, buffering output data, and interfacing the analog core with the host system.