ETD

• cross
• digital signature
• fpga
• hardware accelerator
• post-quantum cryptography
• pqc

The prospect of large-scale quantum computers threatens conventional public-key cryptography. In response, the National Institute of Standards and Technology (NIST) launched a standardization process for additional post-quantum digital signature schemes, in which CROSS was evaluated as a code-based candidate relying on the Restricted Syndrome Decoding problem. This thesis presents a loosely coupled FPGA accelerator for the CROSS v2.2 signing procedure. The accelerator supports the R-SDP and R-SDP(G) variants and all three NIST security categories in the fast optimization corner. The parameterized RTL architecture consists of an orchestrator, shared on-chip memory, and three specialized engines for finite-field arithmetic, SHAKE-based hashing and cryptographically secure pseudorandom generation (CSPRNG), and data packing and alignment. The complete signing flow was validated against official CROSS known-answer tests. Depending on the variant and security category, post-route results on an AMD Zynq UltraScale+ FPGA show 24.6 to 25.9 thousand LUTs, 6.8 to 7.4 thousand flip-flops, maximum clock frequencies between 93.8 and 122.0 MHz, and signature generation times of 1.22-8.23 ms. Compared with the state of the art, the design offers a suitable solution for resource-constrained targets, with lower logic utilization at the cost of higher signing latency. Its parameterization allows some adjustment of the trade-off between resource utilization and performance.