• accelerator
• Cross
• cryptography
• digital signature
• fpga
• hardware
• Nist
• public key
• quantum
• risc-v
• secret key

We live in an era of continuous digital transformation, data is constantly transmitted and potentially modified, making secure communication crucial. This is typically achieved through Public Key Cryptography (PKC) schemes, which rely on computational problems that are hard to solve using classical computers. However, with the advent of quantum computers, classical cryptography systems can be broken by Shor’s algorithm, compromising the security previously provided by PKC. In 2016, National Institute of Standard Technology (NIST) started a standardization process with the aim to select quantum resistant algorithms. To date, NIST has selected only lattice-based and hash-based digital signature schemes and now is interested in other classes of problems, in order to diversify the standardization. For instance, CROSS is a code-based digital signature scheme and is currently candidate for the second round of the Additional Digital Signatures standardization. Compared to classical schemes, It is more computationally intensive, so we proposed a tightly-coupled RISC-V ISA extension, in order to speed-up CROSS. After identifying the performance bottlenecks, represented by vector-matrix product, our work relies on the creation of new instructions executed by the Post Quantum ALU (PQ ALU), a new functional unit directly integrated in the CVA6 core. Using the hardware accelerator developed in this work, we reached a maximum clock cycles reduction of 40% for CROSS signature generation function and 36.6% for CROSS signature verification, with a minimal impact on resource utilization (1017 LUTs and 3 DSP) for the CVA6, implemented on the Xilinx ZCU106 platform using Vivado.