Tesi etd-05082025-154730 |
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Tipo di tesi
Tesi di laurea magistrale
Autore
CARLON, JACOPO
URN
etd-05082025-154730
Titolo
Design and implementation of a mechanism for power-aware packet processing exploiting OS kernel bypass.
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
COMPUTER ENGINEERING
Relatori
relatore Prof. Lettieri, Giuseppe
correlatore Prof. Cucinotta, Tommaso
correlatore Prof. Cucinotta, Tommaso
Parole chiave
- DPDK
- Energy Consumption
- Energy-Efficient
- Packet Processing
- Power Aware
Data inizio appello
27/05/2025
Consultabilità
Non consultabile
Data di rilascio
27/05/2028
Riassunto
Kernel-bypass techniques have evolved with low-latency and high-throughput as main objectives; however, they inevitably come at a cost in terms of power consumption.
This thesis tests and compares different kernel-bypass approaches capable of achieving high throughput with low latency, examining their power consumption against different traffic patterns.
In light of the existing literature on kernel-bypass techniques, this work focuses on different implementations of Data Plane Development Kit (DPDK) for Layer 3 (IP-based) forwarding and studies the trade-off between latency performance (in average, and in 95th and 99th percentiles) and power consumption.
This is done by exploiting CPU idle states (C-States) and different CPU frequencies (P-States) to try and identify some heuristics that allow for a reasonable trade-off between power consumption and latency.
One of the most important results obtained in this thesis is the creation of a "hybrid" implementation, which tries to detect periodicity in the recent traffic pattern and accordingly decides whether to execute busy-polling, short sleeps (usually 1-2 microseconds) or to instead enable interruptions and enter a far more power-saving mode (which incurs in latency cost due upon its waking from deep idle states).
This implementation shows power consumption comparable with the most power-efficient approach, and an average latency which greatly narrows the gap with the fastest but far more power-intensive implementation.
This thesis tests and compares different kernel-bypass approaches capable of achieving high throughput with low latency, examining their power consumption against different traffic patterns.
In light of the existing literature on kernel-bypass techniques, this work focuses on different implementations of Data Plane Development Kit (DPDK) for Layer 3 (IP-based) forwarding and studies the trade-off between latency performance (in average, and in 95th and 99th percentiles) and power consumption.
This is done by exploiting CPU idle states (C-States) and different CPU frequencies (P-States) to try and identify some heuristics that allow for a reasonable trade-off between power consumption and latency.
One of the most important results obtained in this thesis is the creation of a "hybrid" implementation, which tries to detect periodicity in the recent traffic pattern and accordingly decides whether to execute busy-polling, short sleeps (usually 1-2 microseconds) or to instead enable interruptions and enter a far more power-saving mode (which incurs in latency cost due upon its waking from deep idle states).
This implementation shows power consumption comparable with the most power-efficient approach, and an average latency which greatly narrows the gap with the fastest but far more power-intensive implementation.
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