ETD

• DARE
• error logging
• error reporting
• RISC-V

This thesis concerns the analysis and design of an error-logging and reporting Hardware-Software peripheral for RISC-V Architectures. The proposed inteface was designed to log information about hardware errors and expose it to system software through dedicated memory-mapped Error Record Banks, with the goal of improving system Reliability, Availability, and Serviceability (RAS). The interface achieves full compliance with the newly developed RISC-V RAS Error-record Register Interface (RERI) standard, with particular focus on digital components such as the Deferred Errors Controller, meant to manage uncorrected but deferrable errors originating from ECC-protected units. Using a VEC tile (comprising a RISC-V scalar core and a VPU) as a reference platform, the work defines the Glue Logic required to interface SECDED-protected L1/L2 caches and Vector Register File (VRF) with the peripheral. Furthermore, a custom Error Record register was added to provide supplemental contextual information for software RAS handlers, while configuration parameters were introduced to enable a trade-off between logging granularity and hardware overhead. The design was implemented in SystemVerilog, synthesized via Synopsys Design Compiler for area analysis, and functionally verified using ModelSim.