• cgra
• controller
• custom extension
• direct memory address
• dma
• dmac
• estensione
• flexible
• neorv32
• risc-v

The thesis project consists of the design of a direct memory access (DMA) and its controller, which provides speed and at the same time versatility to the system in which it is embedded. While speed is a peculiarity of any DMA since their purpose is to relieve the CPU by allowing peripherals direct access to system memory, versatility is the real novelty compared to State-Of-The-Art: in fact, this DMA is configured so that the memory address and the size of the data packets to be transferred can be changed by changing custom instruction arguments. These custom instructions were implemented by exploiting the RISC-V Instruction Set, which presents the possibility that it can be extended by enabling one of its possible extensions: among these is precisely the custom extension, thanks to which the instructions whose arguments are sent to the DMAs to transfer a certain burst were created. At the end of the paper, in addition to the resources used and compliance with timing constraints, we demonstrate the advantage of using the designed DMA in terms of speed, illustrating a comparison between an architecture with this DMA and without.