• accelerator
• AI
• CNN
• FPGA
• hardware
• layers
• residual

Artificial Intelligence, particularly Convolutional Neural Networks (CNNs), have many applications in biology, medicine, and industry. CNNs are increasingly used on-the-edge, exploiting from FPGA technology for hardware acceleration. Despite FPGA advantages such as reprogrammability and high performance, drawbacks include resource limitations and power consumption, posing challenges for CNNs. FPG-AI, a toolflow for FPGA-based CNN hardware accelerators, aims to address these challenges by customizing the hardware accelerator architecture. Model compression techniques such as quantization, mitigate resource requirements. However, the current FPG-AI lacks support for residual layers, which are crucial for network depth and accuracy. This thesis extends FPG-AI to accommodate residual layers, which requires logic block additions and DMA modifications. The process of residual layers involves storing processed layers in DDR memory portions and enabling specialized blocks for residual layer processing. Simulations confirm proper functionality, though with minor alterations in power consumption, timing, and resource utilization. There is a slight increase in resource utilization and there is also a slight decrease in timing performance. Overall, the residual network extension enhances the capabilities of FPG-AI without significantly affecting its efficiency, confirming its potential to improve CNN performance on FPGA platforms.