• accelerator
• AI
• ARM
• CNNs
• FPG-AI
• FPGA
• framework
• hardware
• HDL
• microelectronics
• NanoXplore
• NG-ULTRA
• onboard
• prototype
• System-on-Chip

Artificial intelligence applications in space have gained ground in recent years, mainly due to the on-board processing of EDGE devices. On-board computing reduces latency and bandwidth costs but poses challenges due to resource and power constraints. In this scenario, FPGAs offer a valuable solution for onboard computing due to their energy efficiency and suitability for artificial intelligence algorithms. Vendors also provide radiation-resistant versions crucial for space missions. However, optimizing algorithms for limited resources can be time-consuming. To address this problem, researchers and companies are focusing on the development of automated AI acceleration frameworks. At present, there is no toolflow to support RHBD FPGAs from Nanoxplore, a European company that has interested the European Space Agency (ESA) in pursuing European sovereignty. For this reason, this thesis aims to provide the first support for these devices by extending the FPG-AI framework, a technology-independent tool developed by the University of Pisa. This thesis focuses on the compatibility of FPG-AI with NanoXplore's NG-ULTRA device, initially implementing LeNet-5 for digit recognition. NiN on the Cifar10 dataset further demonstrated the compatibility of NG-ULTRA even on larger models. An ARM-based SoC for LeNet-5 was designed on NanoXplore's NG-ULTRA DevKit board. Tests were conducted separately for the Processing System (PS) and the Programmable Logic (PL) before loading the final accelerator and software on the board. Verification of system inference was done using Xilinx's ZCU106 board due to lack of documentation, which has not yet been released by NanoXplore. The accelerator was interfaced directly with the PS to emulate the NG-ULTRA's interface situation.