ETD

• ATE
• DSI
• DUT
• failure
• FPGA
• ICE
• MEMS
• pattern
• SoP

The objective of this work is to provide solutions to bridge the gap between the ASIC development and the final ASIC mass production test. In other words here are proposed several innovative automatic low-cost test strategies for VLSI ASIC prototypes verification that can be done directly in house without the necessity to refer to a mass-production device when it should be over dimensioned, because the ASIC is still in its development phase and a full-coverage test procedure hasn’t been developed yet.