logo SBA

ETD

Archivio digitale delle tesi discusse presso l’Università di Pisa

Tesi etd-03182024-145252


Tipo di tesi
Tesi di laurea magistrale
Autore
RIGHETTI, MATTEO
URN
etd-03182024-145252
Titolo
Exploring Model Based Design and High-level synthesis for System-on-Chip FPGA prototyping and testing: A Case Study of NDV Index computation for hyperspectral images
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Prof. Fanucci, Luca
tutor Ing. Aguado, Alberto Urbon
Parole chiave
  • Simulink
  • MATLAB
  • KCU105
  • image processing
  • ILA
  • hyperspectral image
  • high-level synthesis
  • HDL Coder
  • FPGA
  • SoC
  • VHDL
  • Vitis
  • Vivado
Data inizio appello
17/04/2024
Consultabilità
Non consultabile
Data di rilascio
17/04/2094
Riassunto
This study aims to design a block using MATLAB/Simulink capable of taking two images as input, performing an algorithm, and calculating the Normalized Difference Vegetation Index (NDVI) as output. The HDL Coder tool is used to convert the Simulink model into HDL, followed by the creation of a System-on-Chip (SoC) around the IP generated and implementation of the architecture on the KCU105 FPGA.
The validity of the design was tested both in software using Simulink and ModelSim and in hardware using the Integrated Logic Analyzer (ILA), as well as through direct implementation on the board.
Eight different Simulink models were developed to compare them in terms of estimated resource usage and critical path. After verifying the consistency of results in Simulink and ModelSim, two of the models were chosen for hardware implementation. Through the Vitis console, the expected indices can be observed.
File