ETD

• energy filtering
• energy harvester
• nanodevice
• nanostructures
• on-chip
• Seebeck effect
• silicon

This doctoral thesis investigates silicon as a material for thermoelectric energy conversion, focusing on performance optimization through nanostructuring strategies and on-chip device fabrication using CMOS-compatible technologies. Thermoelectric conversion is of increasing interest due to the global need for sustainable waste heat recovery, as 60–72% of produced energy is currently dissipated across industrial, automotive, environmental, and microelectronic sectors.

Thermoelectric devices directly convert heat into electricity via the Seebeck effect, without moving parts or fluids, offering reliability and scalability. However, their large-scale adoption is limited by the lack of efficient, low-cost, non-toxic materials compatible with microelectronics. Silicon, though traditionally considered inefficient for thermoelectric applications, represents a promising candidate when properly engineered at the nanoscale.

The thesis develops two complementary research directions. The first focuses on power factor optimization through doping control and nanostructured multi-barrier architectures based on energy filtering. Periodic potential barriers are engineered along the transport direction via selective doping, enabling enhanced electronic transport mechanisms absent in bulk silicon. Fabricated devices demonstrate that sequential barriers selectively enhance high-energy carrier transport, significantly increasing the Seebeck coefficient without severely degrading electrical conductivity. Supported by transport simulations, the results show a power factor improvement of up to two orders of magnitude compared to bulk silicon.

The second part addresses the design and fabrication of CMOS-compatible on-chip thermoelectric devices based on suspended silicon nanostructures. Using doped SOI substrates and a fully CMOS-compatible process flow—including electron beam lithography, DRIE, selective diffusion doping, and buried oxide removal—the developed architecture minimizes thermal conductivity through phonon scattering and enhanced thermal isolation.

Two configurations were implemented: a uni-leg structure for material characterization and a bi-leg structure for complete generator realization. FEM-based thermo-electric simulations guided the optimization of thermal gradients and reduction of substrate losses. Experimental characterization confirms effective thermal isolation and reproducible device operation, demonstrating the feasibility of monolithic integration of silicon-based thermoelectric generators in advanced electronic systems.