• AES SCA countermeasures
• power analysis
• side-channel attack
• side-channel analysis

This thesis focuses on Side-Channel Analysis (SCA) for hardware implementations of AES. A custom environment has been developed that allows to perform all the necessary steps of a typical SCA flow for a hardware AES module under test. The environment is compatible with the implementation on SAKURA-G board. Three countermeasures have been designed, implemented and evaluated for one of the two AES modules that have been tested on the SAKURA-G board: one uses a scalable combination of TRNGs and shift registers to introduce random transitions (amplitude noise), lowering the signal-to-noise ratio of the sensitive data leakage based on power consumption, another countermeasure uses Wave Dynamic Differential Logic (WDDL) to make the power consumption independent of the processed data and the last countermeasure features a combination of WDDL and amplitude noise. All of the three countermeasures are comparable to the state of the art solutions