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Archivio digitale delle tesi discusse presso l’Università di Pisa

Tesi etd-02012021-145636


Tipo di tesi
Tesi di laurea magistrale
Autore
RICCI, MARCO
URN
etd-02012021-145636
Titolo
Design of side-channel countermeasures for AES hardware implementation and its assessment through a custom side-channel power analysis physical environment
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Prof. Fanucci, Luca
relatore Ing. Crocetti, Luca
relatore Ing. Baldanzi, Luca
Parole chiave
  • AES SCA countermeasures
  • power analysis
  • side-channel analysis
  • side-channel attack
Data inizio appello
19/02/2021
Consultabilità
Non consultabile
Data di rilascio
19/02/2091
Riassunto
This thesis focuses on Side-Channel Analysis (SCA) for hardware implementations of AES. A custom environment has been developed that allows to perform all the necessary steps of a typical SCA flow for a hardware AES module under test. The environment is compatible with the implementation on SAKURA-G board. Three countermeasures have been designed, implemented and evaluated for one of the two AES modules that have been tested on the SAKURA-G board: one uses a scalable combination of TRNGs and shift registers to introduce random transitions (amplitude noise), lowering the signal-to-noise ratio of the sensitive data leakage based on power consumption, another countermeasure uses Wave Dynamic Differential Logic (WDDL) to make the power consumption independent of the processed data and the last countermeasure features a combination of WDDL and amplitude noise. All of the three countermeasures are comparable to the state of the art solutions
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