ETD system

Electronic theses and dissertations repository

 

Tesi etd-06052019-133334


Thesis type
Tesi di laurea magistrale
Author
SERRA, GABRIELE
email address
gabriele_serra@hotmail.it
URN
etd-06052019-133334
Title
Interprocess communication mechanisms and exception handling for a real-time safety-critical kernel
Struttura
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
EMBEDDED COMPUTING SYSTEMS
Commissione
relatore Prof. Buttazzo, Giorgio C.
correlatore Prof. Biondi, Alessandro
Parole chiave
  • arm a53
  • armv8
  • ipc
  • kernel
  • safety-critical kernel
  • exception
  • arm architecture
  • exception handling
  • interprocess communication
Data inizio appello
21/06/2019;
Consultabilità
secretata d'ufficio
Data di rilascio
21/06/2022
Riassunto analitico
In recent years, the need to modernize the railway infrastructure, both in terms of technology and safety, is pushing infrastructure managers towards the design of ad-hoc real-time systems for railway management. This thesis was developed within a project managed by the Scuola Superiore Sant’Anna in collaboration with RFI in which the ReTiS Laboratory is responsible for developing a kernel for a real-time operating system. The objective of this thesis consists of designing and implementing an easy to use, well-isolated and efficient method to enable applications running on kernel at the user level, to communicate in a predictable fashion and further, to let kernel notifies illegal actions performed by tasks. The development of these mechanisms required a substantial effort, first to evaluate and choose the architecture best suited to the needs of railway applications and subsequently to proceed with the actual implementation, keeping in line with the stringent regulations required by the industry to proceed to product software certification. The architecture selected as the reference model is the one described by the ARINC 653 standard, the reference standard for avionics applications. The reference model has been redesigned to adapt it to different needs. Mechanisms were carefully designed to exploit the performance on multicore platforms. Experimental results have been finally performed to validate the proposed approach and assess its performance upon an ARM A53 processor.
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