• fpga-based SoC
• autonomous driving
• Vitis AI
• embedded platforms
• Ultrascale+
• Xilinx
• deep neural networks
• hardware acceleration

Recently, renewed attention to Artificial Intelligence has emerged thanks to algorithms called Deep Neural Networks, which can achieve high performance in performing specific tasks. Nowadays, DNNs can even overcome human accuracy, at the cost of a high computational complexity. GPUs are used to accelerate the training and inference phases of a DNN, but generally determine a very high power consumption. The latter, together with the need of low latency, is critical for power and resource constrained embedded platforms and AI real time applications. GPUs are less attractive for them and therefore there is a growing demand for specialized Hardware Accelerators, which can fit embedded platforms requirements.

This thesis is focused on the DNNs of the Baidu Apollo autonomous driving framework. These models are in Caffe format and optimized to execute on NVIDIA GPUs. In this work, FPGA-based hardware accelerators, one for each Apollo DNN, are proposed and based on the Deep Learning Processor Unit core by Xilinx. The HAs are deployed on a Xilinx Ultrascale+ ZCU102 SoC FPGA platform and implemented using the Vitis AI v1.2 tool, which applies compression techniques, in order to reduce DNN complexity. During the implementation, some issues due to strict limitations of the tool have been faced and solved. Finally, an experimental evaluation has been conducted to evaluate the performance of each DNN, focusing on the resulting throughput expressed in frame rates.