• asynchronous
• GALS
• mesochronous
• Network-on-Chip
• NoC
• System-on-Chip

The number of transistors that can be integrated on the same silicon die doubles every 2 years. As a consequence today it is possible to manufacture more and more complex System-on-Chip including several processing and storage elements. However, deep sub-micron (DSM) technologies imply also some physical issues, known as DSM effects, which force to introduce important architectural changes. The Network-on-Chip (NoC) paradigm has been proposed as a possible solution for designing scalable and flexible on-chip communication infrastructures in new generation technologies. While technology scales down, the interconnection delay becomes significant and in some cases increases. This issue is known as wire-delay problem and it is one of the most limiting deep submicron effects. In order to allow the implementation of complex SoCs with reasonable time-to-market, NoCs have to rely on efficient Globally Asynchronous Locally Synchronous (GALS) architectures able to simplify the timing convergence and to efficiently allow the integration of deeply different IPs. Another challenge consists in finding solutions for designing high-performance and low-power on-chip memories suitable for the implementation of large level-two caches in single and multi-processor architectures. The Non Uniform Cache Architecture (NUCA) paradigm is the chosen solution to reduce the negative effects of the wire-delay on the memory access time. In this work an effective GALS Network-on-Chip architecture to reduce deep submicron effects in complex SoCs is proposed. Such architecture has been mainly developed for the Versatile-STNoC (VSTNoC) solution, the STMicroelectronics Network-on-Chip already used in a manufactured complex SoC for HDTV applications. It is expected that this approach will drastically simplify timing convergence, enabling the implementation of complex functionalities and introducing big benefits in terms of time-to-market and performance. An alternative NUCA design to implement large on-chip level-two caches is also proposed. This solution, known as TD-NUCA, is particularly suitable for application specific domains, in order to minimize silicon area, maximize performance and reduce power consumption.