ETD system

Electronic theses and dissertations repository

 

Tesi etd-03272019-235026


Thesis type
Tesi di laurea magistrale
Author
FONTANA, ANTONINO GIUSEPPE
URN
etd-03272019-235026
Title
Design and verification of STM32 digital IP cell for SPI and I2S interfaces
Struttura
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Commissione
relatore Prof. Fanucci, Luca
tutor Ing. Guarnaccia, Giuseppe
Parole chiave
  • STM32H743ZI microcontroller
  • NUCLEOH7 board
  • I2S
  • SPI
  • STM32
Data inizio appello
03/05/2019;
Consultabilità
secretata d'ufficio
Data di rilascio
03/05/2022
Riassunto analitico
This thesis comes from a six months internship in STMicroelectronics, Catania site. It has been taken into account the analysis of the digital Intellectual Property module of SPI2S peripheral and the verification of its main and advanced features in simulation and directly on silicon in order to collect a precious feedback to find any problems and/or limits and so to correct bugs and make appropriate changes. The aim of this work has been to gain experience in SoC design and embedded systems with particular focus on STM32H7 microcontroller, to study the functionality and the RTL(Register Transfer Level) code of the last version of SPI2S peripheral IP, to know how to use a simulation environment as Cadence SimVision Debug tool, to develop a software in C language to stimulate a phisical realization of the interface in several different configurations using Atollic TrueSTUDIO IDE.
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