• automotive
• cryptography
• network
• security
• vlsi

The research reported on in this thesis focuses on efficient solutions to address challenges in the design of electronics systems for automotive security. Specifically, this thesis describes three research activities focused on innovative solutions for in-car network data protection and authentication.
The first research activity addresses the implementation of the IEEE 802.1AE MAC Security (MACSec) standard for automotive Ethernet backbones. The work was mainly focused on the research and evaluation of the trade-offs for an implementation suitable for the automotive industry. Specifically, a flexible solution was designed with particular attention to reducing the latency and the area of the system. The 100 Mbps, 1 Gbps and 10 Gbps Ethernet speeds were addressed to allow the latest multimedia functionalities. The system was designed and synthesized using a 40 nm standard-cell CMOS technology.
The second research activity focuses on the design of hardware accelerators for the IEEE 802.1X-2010 standard. The IEEE 802.1X-2010 standard describes the authentication phase for IEEE 802.1AE, but it cannot be implemented for automotive applications using existing software applications. After identification of the time-intensive kernels of the software modules, this part of the study proposes a hardware solution to speed up the slowest sections. Accelerators were implemented on a 40 nm standard-cell CMOS technology in order to allow for easy integration with the MACSec architecture.
The third research activity is dedicated to an innovative implementation of the Secure Hardware Extension (SHE) to protect parameters for in-car cryptography and to authenticate software routines. The key aspect of innovation is the implementation of an efficient and detailed architecture to fulfill all the requirements of the SHE. Furthermore, optimizations to meet the modern security requirements of the automotive world are proposed and analysed in detail. The hardware architecture of the system and its software interface were jointly designed and optimized for efficient and flexible implementation. The system proof-of-concept was implemented on a Xilinx Zynq 7000 System-on-a-Chip to verify the functionalities, the hardware-software interfaces and the size of the circuit.