• analog-to-digital conversion
• CMOS
• delta-sigma converter
• Integrated circuits
• noise-shaping
• oversampling
• ultra-low-power

The increasing need of digital signal processing for telecommunication and multimedia applications, implemented in complementary metal-oxide semiconductor (CMOS) technology, creates the necessity for high-resolution analog-to-digital converters (ADCs). Based on the sampling frequency, ADCs are of two types: Nyquist-rate converters and oversampling converters. Oversampling converters are preferred for low-bandwidth applications such as audio and instrumentation because they provide inherently high resolution when coupled with proper noise shaping. This allows to push noise out of signal band, thus increasing the signal-to-noise ratio (SNR). Continuous time delta-sigma ADCs are becoming more popular than discrete-time ADCs primarily because of inherent anti-aliasing filtering, reduced settling time and low-power consumption.
In this thesis, a 2nd-order 4-bits continuous-time (CT) delta-sigma modulator (DSM) for radio applications is designed. It employs a 2nd-order loop filter with a single operational amplifier. Implemented in a 65-nanometer CMOS technology, the modulator runs on a 0.8-V supply and achieves a SNR of 70dB over a 500-kHz signal bandwidth. The modulator operates with an oversampling ratio (OSR) of 16 and a sampling frequency of 16MHz.
In the first chapter the principles of ΔΣ modulators are analysed, introducing the differences between discrete-time (DT) modulators and continuous-time (CT) modulators. In the next chapter the techniques to design a ΔΣ modulators for ultra-low-power radios are presented. The third chapter talks over the design of the operational amplifier, which appears inside the loop filter. In the fourth chapter the performance of the complete ΔΣ modulator, which employs a flash quantizer, is shown. Finally, in the last chapter, a performance analysis is carried out replacing the flash quantizer with an asynchronous SAR quantizer. The analysis shows that a further reduction of the quantizer power consumption of about 40% is possible. The conjunction of this replacement with the power-saving technique implemented in the loop filter appears relevant.