We address the gap between structured parallel programming and parallel architectures by formalizing a cost model for shared memory architectures. The cost model captures most of architectural details (processors, memory hierarchy, interconnection network, etc.) to evaluate the under-load shared memory access latency. Analytical and Numerical resolution techniques will be provided and compared. The former ones will be based on Queueing Theory. The latter ones will resort on Markov Chains constructed by means of the stochastic process algebra PEPA.