• LHCb
• real-time
• reconstruction
• trigger

In the past four years the LHCb experiment has been extensively upgraded (Upgrade I) and it is now taking data performing a full real--time reconstruction of all collision events at the LHC average crossing--rate of 30 MHz.
At the same time an even more ambitious upgrade is already being planned (Upgrade II) and intense R&D is ongoing to boost the real--time processing capability of the experiment.
The instantaneous luminosity will increase by a factor of 5-10 and the trigger system should deal with data coming from more granular and complex detectors.
In an effort of moving reconstruction and data reduction to the earliest possible stages of processing, heterogeneous computing solutions are being explored, including a highly--parallelised custom tracking processor based on the "Artificial Retina" architecture.
The "Artificial Retina" architecture takes advantage of FPGA parallel computational capabilities, by distributing the processing of each event over an array of FPGA cards.
As a proof-of-concept of the technology, a life-size demonstrator for the reconstruction of pixel tracking detectors is being realized, implemented in commercial, PCIe hosted, FPGA cards.
These cards are interconnected by fast optical links and they operate parasitically on live LHCb data from Run 3.
In this thesis, I describe the optimization of the switch needed to efficiently deliver hits to the various FPGA boards and I demonstrate the feasibility of the system given the current hardware constraints