• analog front end
• analog integrated circuits
• electronic nose
• gas sensor
• PCS
• read-out circuit

Monitoring and detecting several gas concentrations in the environment is becoming more important every day, especially from the point of view of collective health and well-being. For this reason, a lot of research and studies are focused on the improvements of gas sensors. Gases of particular interest include oxygen (O2), carbon dioxide and monoxide (CO and CO2), nitrogen oxide (NOX) and volatile organic compounds (VOCs). When multiple gases are detected by a single sensor, it is usually referred to as an electronic nose. These sensors can be employed in different area of interest like agricultural, medical and industrial. The typical sensing system is made up of a number of different discrete and distinct sensor technologies that combine a discrete gas sensing element with a separate drive and signal conditioning circuit. This results in big, stiff, power hungry and expensive sensors.
NXP has recently conceived a novel method for detecting gas through the changing in capacitance. Capacitive sensors are attractive because they do not consume static power and they allow the sensor to be integrated in a single IC with the read-out circuitry, and to be sensitive to several different gases. The proposed sensing technique developed by NXP uses compact sensing nodes, called pixels, to detect several gases, hence the name Pixelated Capacitive Sensor. These pixels are collected in matrixes and are placed on top of the last metal layer of the IC. They are covered by different inks, each of these sensitive to a particular gas, which are printable materials that change their dielectric properties when they absorb gases or VOCs. The Pixelated Capacitive Sensor is embedded into a microcontroller, from the family of NXP low power microcontrollers, which provides signal processing of the measured signals.
In this thesis a new read-out circuit for the Pixelated Capacitive Sensor in 140nm CMOS has been designed. This read-out circuit performs a capacitance-to-time conversion and is made up of several sub-circuits, a common-gate amplifier, a comparator and a finite state machine. The architecture implemented is running at 50MHz and performs a single ended reading.
The value of the capacitance of a single pixel is read using two switches controlled by two non-overlapping clocks that discharge and charge the value of the capacitance to the discharge potential and the transfer one. The cascoded Common Gate Amplifier (CGA) that follows, controls the column voltage and passes the column current to an integration capacitor. The integration period, that starts opening the reset switch, which controls the voltage across the integration capacitor, lasts until the voltage on the bottom plate of the integration capacitor reaches a defined voltage, that is the negative input voltage of the comparator. When the positive input of the comparator arrives at a lower voltage than the negative one, the comparator triggers and the output signal, that has now become 0, is sent to a clocked Finite State Machine (FSM). The clocked FSM is used to control the switch which restores the voltage across the integration capacitor.
The analysis done for the power consumption of the analog blocks designed shows a total power consumption of 15.366uW and the one done for the SNR a value of 61.78dB.