• ARM
• cache interference
• hardware monitoring
• hardware partitioning
• memory interference
• memory partitioning
• memory performance
• memory performance requirements
• MPAM
• quality of service

To address their ever-growing performance demands, computing systems have been evolving towards increasingly heterogeneous and thus complex architectures in which memory resources are distributed across multiple domains connected by networks-on-chip. This, however, has led to a steady decline in their memory performance predictability and thus in their capability to provide Memory Performance Guarantees, a key factor in many modern application domains relying on a minimum Quality of Service and/or stringent safety requirements such as cloud computing, Industry 4.0, automotive, robotics and augmented reality.
To tackle this problem, in recent years ARM released the Memory System Resource Partitioning and Monitoring (MPAM) specification, which defines a set of hardware partitioning and monitoring mechanisms that can be implemented in memory components and configured via software to enable system designers to enforce memory performance requirements – an approach presenting the potential of a widespread adoption given the company’s market penetration in many application domains.
In this thesis we define a mathematical framework modelling the Memory Performance in average terms of hardware and software components capable of explicitly characterizing their Memory Interference contributions. We then build upon such model a description of the memory performance metrics and cost associated with using the MPAM memory partitioning mechanisms and define two complementary strategies of using them to meet memory performance requirements.
Next, we propose a set of monitoring extensions aimed at enriching the memory performance information available in a system, both at the design stage and at run-time. In particular, we put forward an approach which, to the best of our knowledge, is the first of its kind enabling the direct evaluation of the memory interference degree suffered by tasks in using a cache component.
We conclude by propounding two advanced run-time approaches to enforcing memory performance requirements and enhancing the system’s overall memory efficiency and thus performance, with a more precise definition being left to future work.