• alignment
• cdr
• CERN
• clock recovery
• DDMTD
• digital design
• FPGA
• HPTD
• jitter
• oscilloscope
• phase
• phase determinism
• phase interpolator
• phase measurement
• phase noise
• phase stability
• picosecond
• pll
• Python
• rxrecclk
• rxusrclk
• timing distribution
• transceiver
• Verilog
• VHDL
• Vivado
• Xilinx

At CERN high precision phase stability is a new concern due to the high luminosity upgrade for the Large Hadron Collider (HL-LHC), which will occur in 2025. The electronic systems that elaborate data from the detectors need to be synchronized with the collisions of particles. The Bunch Clock is the occurrence rate of those collisions. It is distributed from RF cavities, where particles get accelerated, to the four experiments, located kilometers away. This clock travels through fibers and reaches the back-end of the experiments, where FPGAs distribute it through various nodes until it reaches the radiation hard front-end.
This thesis presents my contribution for a project undertaken by the CERN's High Precision Timing Distribution team with the goal to implement and evaluate a new method to achieve a picosecond-level phase determinism in the Xilinx transceivers of the back-end's FPGAs in charge of the Bunch Clock distribution.
In a multi-hop system for timing distribution the clock is embedded in serial streams. It is recovered from received data and used as a reference for the next link, thus maintaining synchronization.
One issue affects the recovered clock after the reset of the receiver, the reset causes a random phase jump on the recovered clock reducing phase determinism.
The project aims to implement a measuring systems for phase jumps and eventually to apply a phase correction.
The proposed solution involves adding an external high speed fanout to the data stream to bring the reference clock directly in the FPGA fabric without passing through the transceiver. It is then compared with the recovered clock via the CERN DDMTD IP, which measures a phase difference. After the phase correction the improvement on phase determinism is by a factor of 3, reaching 1ps RMS.
Different setups with two FPGAs (transmitter and receiver) are built and it is demonstrated that the Digital Dual Mixer Time Difference (DDMTD) is a reliable method of measuring these jumps. Another solution based on the use of an early recovered clock instead of the fanout is proposed and discussed.
A complete multi-hop setup is built with three FPGAs, implementing the above-mentioned techniques to mitigate the detected phase shift and reach the targeted phase determinism of a picosecond.
The developed techniques can be adopted by the technicians of the experiments to address the High-Lumi requirements.