• data acquisition
• FPGA
• HPS
• PET
• SoC

Positron Emission tomography (PET) is a nuclear medical imaging technique which allows non-invasive quantitative assessment of biochemical and functional processes. Its purpose is to determine the distribution of radioactive tracers, chosen depending on the tissues and organs of interest, injected the patient body. The physical principle behind the PET is the detection of the two photons generated by electron positron annihilation due to a β+
decay. The PET is one of the most useful tools to investigate the biology for cancer and cardiac disorders, and to perform molecular imaging. Its best feature is sensitivity: it is the most sensitive technique for medical molecular
imaging. This thesis aims at proposing a method for improve the count rate performance of the IRIS PET scanner, a new preclinical system developed on the Department of Physics at the University of Pisa. The IRIS scanner is a
data acquisition system based on FPGA (Field Programmable Gate Array) developed with an high modularity and flexibility. It is composed by 16
detectors, 16 data acquisition boards (DAQ) and 1 motherboard. As of today, the detectors are able to count 0.8·106 single events per second,
while the DAQ boards are able to transfer to the motherboard the data produced by 0.8 106 counts per second and the motherboard is able to transfer
to the Host-PC the data produced by 1.1·106 counts per second. Thus, the maximum rate of photons that could be detected is 0.8·106 photons per second. For a PET scanner, this maximum rate is very important because place limits
on the sensitivity and on the Noise Equivalent Count Rate (NECR) of the system and its performance when a tracer with a high activity is used. The bottleneck is given by the detectors and by the link between the DAQ boards
and the motherboard. Research for improve the detectors are planned, thus my study has been focused on improve the link between the DAQ boards and the motherboard and the link between motherboard and Host-PC.
In order to upgrade the first link, a new protocol for the data transfer has been
investigate. This upgrade would be poorly invasive because does not require hardware changes. To implement this new protocol some firmware components have been developed. After a complete simulation, these components were integrated in the DAQ and the motherboard firmwares. Several tests were made for verify the data integrity and the data transfer performance.
In order to upgrade the link between the motherboard and the Host-PC, the performance of a new family of FPGA was investigate. The main characteristic of this FPGA family is the integration of an Hard Processor System
(HPS) in it. The combination of FPGA and HPS is very powerful because it allows to implement custom logic in the former and use the latter for
high level control. High-throughput data paths between the HPS and FPGA fabric provide interconnect performance otherwise infeasible with dual-chip solutions.
The board used for test the performance of this new platform is the general purpose prototyping board Arrow SoCkit. A separated set of firmware components has been developed to implement the
communication interface between the FPGA and the HPS. Also, a separated set of driver has been developed to control these components through the
HPS. Several test was made for verify the data transfer speed. The HPS-FPGA bridge was tested with a loop-back through two 64 bits FIFOs components. Eventually, a Ethernet test has been conducted to measure the data transfer
speed between the HPS and the Host PC.
The results obtained are: a 30% performance improvement on the link between the DAQ boards and the motherboard without any hardware changes;
a potential 200% performance improvement reachable with the change of the FPGA family. The maximum count rate reachable with the firmware change is 1.1 Mcps, while the maximum count rate reachable with the change of the FPGA can potentially becomes 3.5 Mcps. Currently, with the implementation of the new firmware the bottleneck becomes the FPGA-Host link, but when a data acquisition system based on the new FPGA family will be developed the bottleneck will become the detectors. Thus, developments to improve the detectors speed will be necessary in the
future.