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Archivio digitale delle tesi discusse presso l’Università di Pisa

Tesi etd-09172019-090459


Tipo di tesi
Tesi di laurea magistrale
Autore
SEVERIN, DAVIDE
URN
etd-09172019-090459
Titolo
Verilog-A model development of a linear regulator with AI based autonomous optimization
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Prof. Bruschi, Paolo
Parole chiave
  • machine learning
  • linear regulator
  • differential evolution
  • AI
  • VerilogA
Data inizio appello
14/10/2019
Consultabilità
Tesi non consultabile
Riassunto
This thesis's purpose is to develop a Verilog-A model of a linear regulator with reference to a 5V transistor-level DC-DC converter. Parameters are added to make the model versatile and re-usable for different use-cases, so that designer are supported in developing new devices and verification engineers in validating top schematics with a considerable saving of time. Generalized Differential Evolution is employed to fit the output waveforms: this powerful Artificial Intelligence algorithm provides all the tools to obtain the best solution under every requirements.
The final solution attains an overall mean accuracy error of less than 0.5% for DC analysis in regulating region, 25% for transient analysis but a computational time reduction of more than 90%. The model functioning is validated in a boost top schematic simulation.
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