• Boost
• CMOS
• DC-DC Converter
• Fully-Integrated
• Self-Oscillating
• Step-Up
• Switched-Capacitor
• Voltage Doubler
• Voltage Tripler

Wireless Sensor Nodes will be the driving force to push the IoT into new applicable domains. Efficient power solutions for WSN are one of the most required innovations.
Since battery replacement is expensive or even prohibitive (in terms of maintenance costs), energy scavenging from ambient becomes the most attractive option.
Scavenging from temperature differences, sunlight or vibration can be accomplished with different devices. These transducers are capable of generating low voltages in the range of 200-500 mV, with great variability, hence, they're not suitable to directly supply the Sensor circuitry (Analog/RF, DSP) Front-End.
Toward that end, efficient power management integrated circuits are needed. Different solutions already exist based on two architectures: Inductance-based switching converters which require the use of off-chip inductive elements or transformers and capacitances yielding high power throughput (using off-chip components allows for very large capacitors to be employed), and CMOS fully-integrated switched-capacitor DCDC converters which have limited output power capabilities but are best suited for small form-factor on-chip power management.
To the best of our knowledge, all existing solutions suffer the same problem. Peak Efficiency is achieved only for a nominal (by design) operating point (VDD,Io,Vo). If the input voltage or the output load current varies, efficiency drops quickly. To make things even worse, when operating at very low input voltages, transistor switches operate in deep subthreshold. Therefore, to achieve a voltage conversion at usable levels, the conversion ratio 1:M should be high enough, with very large transistors.
In such a taxing context achieving high end-to-end efficiencies becomes a bold requirement.
This thesis explores the design space of a new class of converter architectures, the Self-Oscillating Switched-Capacitor DCDC converters.
The circuital complexity of such converters is much higher compared to classical architectures, but they can achieve high and flat efficiency characteristics. The designed converters have on-chip control to implent a context-awareness operation, therefore self-adapting to different operating conditions.
A voltage tripler based on a modified 1:3 ladder converter, with control circuit, has been proposed that can operate with efficiencies up to 70% under different input/load conditions. Also a voltage doubler module has been designed, optimized and laid out. The control circuit operation is based on three core blocks, a dynamic comparator, an incremental charge regulator, and control logic acting as the intermediate digital interface between the comparator and the charge regulator. The voltage doubler achieves 80% peak efficiencies.