• figures of merit
• GRID
• clock recovery
• error protection
• radiation hardness
• space applications
• computing cluster
• client
• sockets
• server
• Python
• C++
• ATLAS
• CMS
• test plan

This thesis is part of the FF-LYNX project, undertook by DII-IET (Pisa) and INFN (Pisa) and relying on a collaboration with CERN (Geneva), and focuses on the development of a high-level SystemC model and simulator of a new communication protocol and interfaces to be used in the context of High Energy Physics (HEP).
The FF-LYNX protocol is meant to provide the diverse and heterogeneous world of HEP experiments with a standard solution to common problems, such as Data Acquisition (DAQ) and Timing, Trigger and Control (TTC). The particle detectors used in HEP experiments generate unwieldy amounts of data following a particle collision (10 TB/s - 1 PB/s). To reduce the amount of data to shift from the detector to the central elaboration system a filter is applied. After a collision the detectors send only a small share of data to the central system. This data is used to ascertain whether the detectors caught interesting events (which are only a few percent of the total). If the results are positive a trigger signal is sent to the detectors to command the acquisition of the interesting events only. This way the data rate becomes manageable. Every HEP laboratory has developed its TTC/DAQ protocol, so no standard solution exists.
FF-LYNX aims at defining a standard but flexible approach that could be employed in all the HEP contexts, therefore enabling savings on money, time and efforts.
The proposed protocol sits at the data-link layer of the ISO/OSI stack, is serial and synchronous and makes use of Time Division Multiplexing to fit two channels in the same wire. One of these channels carries triggers, frame headers and synchronisation patterns, while the other transports data frames. Triggers undergo a scheduling process to make sure they have fixed and known end-to-end delay (a key requirement in HEP experiments).
The high-level simulator has been used to validate the performance of the protocol and to support critical implementation decisions, such as the mechanism for keeping the receiver and transmitter synchronised. A useful set of guidelines have been thus provided for the development of a lower-level VHDL model. The scalable and modular architecture of the simulator will allow it to be reused to control the FPGA emulator that will implement the interfaces at a later project phase.