• relaxation oscillator
• I-C oscillator
• process sensitivity
• temperature sensitivity
• PVT-compensated current reference
• phase noise

Innovative applications, such as wearable and implantable electronics, are causing an increasing demand for fully integrable frequency references. To the purpose of improving their reliability, which is typically lacking with respect to more traditional solutions, their design has to be explicitly oriented to reduce the PVT (Process-Voltage-Temperature) variations of the oscillation frequency. This work focuses, in particular, on the reduction of the process and temperature sensitivity, with the aim of developing a relaxation oscillator with appreciable performances as for its frequency accuracy and stability. The proposed approach consists in the use of a comparator-based I-C relaxation oscillator core supplied by a PVT-compensated current reference, able to produce a reference current independent from the MOSFET threshold voltage. As for the oscillator core, various possibly original circuit variants were taken into account, increasingly more effective in rejecting the frequency errors caused by the comparator hysteresis, delay and threshold noise. Specifically, a dynamic feedback-based compensation technique, adjusting the comparator thresholds on-the-fly so that to eliminate such frequency errors, was eventually developed. The Cadence Virtuoso design tool was used to validate, through electrical simulations, all the proposed circuit implementations, employing device models of the 0.18µm CMOS process UMC 180 MM/RF.