ETD

Archivio digitale delle tesi discusse presso l'Università di Pisa

Tesi etd-09062019-093027


Tipo di tesi
Tesi di laurea magistrale
Autore
BRUNI, FRANCESCO
URN
etd-09062019-093027
Titolo
Design of an asynchronous RISC microprocessor
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Prof. Bruschi, Paolo
correlatore Prof. Piotto, Massimo
tutor Ing. Castellano, Marco
Parole chiave
  • Matlab-Simulink
  • asynchronous
  • RISC microprocessor
  • sensor applications
  • Speed Independence
  • Petri Net
  • delay lines
  • digital design
Data inizio appello
14/10/2019
Consultabilità
Non consultabile
Data di rilascio
14/10/2089
Riassunto
Asynchronous digital logic can show significant advantages in terms of power consumption and speed with respect to the synchronous one. Starting from the state of the art in asynchronous digital logic design and the STMicroelectronics flow for asynchronous finite state machines, a prototype of asynchronous RISC microprocessor oriented to sensors applications has been developed. The proposed architecture has been widely tested and optimized both at high-level, using the Matlab-Simulink environment, and at low-level, with the aid of digital and analog simulators. The obtained design is expected to have an energy consumption per elaboration comparable to its synchronous functionally-equivalent counterpart, but with a speed of operation up to 4x higher. The realization of a test-chip will soon allow to validate these estimates.
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