Tipo di tesi
Tesi di laurea magistrale
Titolo
DESIGN AND MODELLING OF AN ASYNCHRONOUS DIGITAL CONTROLLER FOR BUCK DC/DC
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Riassunto (Italiano)
The aim of this thesis is to perform logical synthesis of a state machine and study its behavior when used as control logic for a buck converter.
Today's converters operate in different modes to achieve high efficiency for a wide range of loads; therefore a control logic based on a state machine is needed in order to maintain high buck efficiency.
Asynchronous digital logic can show significant advantages in terms of power consumption and speed with respect to the synchronous one.
Based on the state of art in asynchronous digital logic design, STMicroelectronics cells were studied and logic synthesis of an asynchronous finite state machine was performed. A mathematical model has been designed to test the functional coverage of the finite state machine. Using the Verilog-AMS language, a buck mixed-signal environment was developed to test how the finite-state machine affects the behavior of the buck, allowing it to operate in different modes.
