• asic
• digital design
• verification
• systemverilog
• uvm
• spacewire
• space
• satellite

The improvement of CMOS technology allows building increasingly complex digital circuits, but new technological nodes bring a raise in the manufacturing cost of a design. Therefore, it's important to pursue “first spin success”, because a re-spin costs money, but also because the company could miss the product's market window while the project is fixed.

To check whether a design is compliant to its specifications, the verification phase is essential and shall be carried out efficiently by planning as many tests as needed. By verifying many different communication protocols, it can be noticed that these tests are very similar between them. This means that different protocols require a similar testbench architecture, so it is possible to draw a general architecture that doesn't require much customization to adjust to each one of them. The Universal Verification Methodology (known as UVM) is a verification methodology created by the Accellera Systems Initiative Organization with the aim of defining a shared methodology supported by the main producers of Electronic Design Automation tools. In fact, Accellera is a not-for-profit organization composed of companies involved in the Electronic Design Automation software (EDA) market and is aimed to promote standards. Thanks to the partnership with IEEE, these standards usually becomes widely adopted among the industry. UVM consists of APIs, classes, guidelines for the SystemVerilog language (IEEE 1800). It allows verification engineers to start from common a base adding just the case-specific functionalities to carry out verification. Engineers can structure a verification environment starting from a configurable layered architecture. Two of the main advantages of using UVM are increased efficiency and better code reuse between projects.

A satellite is composed of many subsystems such as imaging systems, data storage, sensors, processing units, radars, telemetry and so on. These components need to communicate through an onboard network to allow satellite to work properly. For this reason, many communication protocols exist to define how an onboard link needs to work. One of these is called SpaceWire and is promoted by the European Space Agency in collaboration with space agencies such as NASA, JAXA, Roscosmos, private companies and universities. The standard has been released in 2003 and since then many space agencies and companies have adopted it as primary communication protocol onboard satellites. Currently there are hundreds of scientific and commercial satellites from many companies and agencies using SpaceWire for internal network, proving its benefits. The SpaceWire standard defines a high-speed, flexible, full-duplex, serial link. It can be used as a simple point-to-point connection or in conjunction with one or more routing switches. A routing switch is an active network element responsible for managing complex SpaceWire networks. It is especially useful for reducing cables count and ports number on each module. The main advantages of using SpaceWire as primary onboard communication protocol are lower size, weight and costs due to cables, an improved system reliability and an easier integration of satellite modules.

This thesis work starts by introducing concepts regarding digital design, hardware description languages, functional verification and its related tools, the Universal Verification Methodology (UVM) and the SpaceWire standard. The following chapters describe these topics in detail, explaining how the Universal Verification Methodology can be implemented in a real project, and how its components can be developed in this application. The Device Under Verification, which in this project is the SpaceWire Codec IP Core, is an Intellectual Property (IP) owned by IngeniArs S.r.l.. Before starting to build the verification environment, it is necessary to write a detailed verification plan. This document is important to properly carry out the verification, so it is described in detail to prove how it useful in driving the subsequent work. Then UVM and SpaceWire concepts are blended together in a chapter that describes design choices that led to the final architecture of this project. So, this chapter describes the building blocks of the environment, the workflow to follow and, in general, all the significant steps to carry out on order to complete this thesis activity. Finally, the last part of this document highlights the results, performances, and improvements that this work adds to the already existing reality.