• 28nm
• cmos
• dco
• digitally controlled oscillator
• rf

The aim of this work is to present the analysis, design, and implementation of an integrated Digital Controlled Oscillator in an all-digital FLL. The DCO, designed with TSMC28 nm CMOS technology, is conceived to operate from hundreds of MHz to 3 GHz.
The analysis and the design of a nMOS transistor-based DAC and different topologies of Ring Oscillator, will be presented and evaluated in this thesis, leading to the choice for the Pseudo Differential based DCO.
The chosen DAC is a binary weighted current source made with nMOS transistor; it generates a binary weighted current that will drive the oscillator, in this way the output frequency is a function of the output current of the DAC and so of the Digital Control Word.
The DCO is designed to operate up to 5.5 GHz to ensure the correct frequency specifications even with PVT analysis.
The post-layout results estimate, at maximum theorical frequency of 5.5 GHz, a 35% frequency reduction in the output signal.