ETD system

Electronic theses and dissertations repository


Tesi etd-08222017-181549

Thesis type
Tesi di laurea magistrale
Design, development and testing of a PCIe based embedded system for a SpaceFibre Link Analyzer
Corso di studi
relatore Fanucci, Luca
relatore Foglia, Pierfrancesco
relatore Leoni, Alessandro
Parole chiave
  • space
  • embedded
  • ARM
  • Ingeniars
  • SpaceWire
  • communication
  • space
  • bandwidth
  • Xilininx
  • LinkAnalyzer
  • SpaceWire
  • FPGA
  • PCI
  • PCIexpress
  • PCIe
  • SpaceFibre
Data inizio appello
Data di rilascio
Riassunto analitico
The modern space missions need high transmission rates, due to the higher complexity and the fast increasing amount of data to elaborate. The current standard of communication is SpaceWire, but it no longer allows to meet the required transmission rate. It can in fact reach the speed of 200 Mbps, where the new missions need rates in the order of Gbps. For instance, the spacecraft has to take many images in high quality, which must be transferred from the camera to the payload data processing entities in a reasonable time. Moreover, spacecrafts are exposed to a high radiation intensity and there are no commercial solutions available. The successor of SpaceWire is SpaceFibre, which can reach the speed of Gbps. The SpaceFibre standard is supported by the European Space Agency (ESA) and provides QoS, Fault detection, isolation and recovery mechanisms. Therefore, being the new SpaceFibre-based devices more complex, their development needs appropriate tools. For this purpose, an ARM-based SpaceFibre LinkAnalyzer has been developed. This thesis is focused on the design and implementation of a PCIExpress communication system from Host PC to LinkAnalyzer device. The host can generate many data to send on the SpaceFibre link in real-time, so the developers can test the behaviour of their devices on a saturated link. The first part of the thesis is an introduction of the subjects involved like the PCIe, RIFFA library, etc. The main efforts of this thesis are split in 2 phases: the first phase is the hardware side, where the IP to integrate with the LinkAnalyzer project is implemented. The second phase is the software side, here the drivers are implemented and the application code is updated, in order to work with the PCIe. After these two phases, it has been tested whether the Host by LinkAnalyzer can saturate the SpaceFibre link in real-time.