• receiver
• pam
• linearity
• adc
• th
• track and hold

Over the last few years, the strong increment in internet traffic led to a huge amount of transferred data. Contrary to what we might expect, the vast majority of the data traffic is not between the user and the data centers but it is between and inside the data centers themselves. The communications in these environments can reach speeds of 100Gbit/s over a single channel. To achieve such speeds, the data transfer is performed through serial links which make use of serializer deserializer (SerDes) transceivers that take in parallel data, transfer them through a serial signal into the link, and re-parallelize the signal at the receiver side. The transceivers are typically based on digital signal processor (DSP) to exploit the high power and area efficiency of scaled technology nodes. On the receiver side, the signal needs to be converted from the analog to the digital domain to be elaborated and this is performed through high-speed analog-to-digital converters (ADC) implemented with a time interleaved (TI) architecture to achieve the desired sampling speed.

As of now, these receivers use the Pulse Amplitude Modulation with 4 symbols (PAM-4), which receive one of four voltage levels (symbols) each encoding two bits, instead of the Non-Return-to-Zero (NRZ) modulation, which sends a series of two symbols corresponding to zeros and ones, allowing increasing the data rate using the same bandwidth. As the need for faster communications arise, new ways to improve the data rate are researched. The data transfer can be increased by either improving the symbol rate, which is limited by the low-pass behavior of the channel bandwidth or using a higher order modulation like increasing the number of symbols. Examples of these modulations are PAM-8, and other eight symbols modulations that increment the data rate by 50% compared to PAM-4, while using the same symbol rate. However, the smaller eye aperture of PAM-8 compared to PAM-4 or NRZ makes this modulation format very sensitive to noise, non-linearities, and residual inter-symbol Interference (ISI).

These non-idealities directly affect the Bit Error Rate of the receiver, reducing the performance of the overall link. While the noise can be theoretically traded for power consumption of the analog front end and the ISI can be compensated by more complex equalization techniques, the non-linearities are difficult to address. Due to the low supply voltages of scaled CMOS technology nodes, it is challenging to achieve a high voltage swing for a good Signal-to-Noise Ratio (SNR) while maintaining a suitable Total Harmonic Distortion (THD).

To reduce this issue, the need arises for a highly linear track and hold (T&H) sampling stage of TI ADCs, which is one of the less linear components of the converter. This component not only need to have low distortions, but it also needs a good bandwidth due to the high frequency signal employed. In addition, in TI track and hold circuit the design of the clock distribution network is critical to maximize the performance of the circuit. The skew correction (necessary in these networks) of the clock signal is typically operated by variable delay lines. However, delay lines usually introduce the highest jitter contribution to the clock distribution chain. The sampling time jitter degrades the SNR when the ADC is converting high-frequency signal components. Therefore, the delay lines are required to have low time noise which translates into a power-noise design trade-off. While two delay line topologies are mainly used in literature, no performance comparison is provided to show which topologies have the better power-noise trade-off.

Moreover, in the receiver, other components can introduce distortions that degrades the linearity and vary with process, temperature and voltage. To overcome this the need arise for a calibration of the static non-linearities of the circuit. In this thesis, I will first propose a new T&H buffer circuit that is more linear than conventional T&H circuits and with embedded sampling switches. Then, a study is performed to demonstrate which is the delay line with the highest power noise efficiency to maximize the jitter performance of the clock distribution network. Afterward, a second stage T&H buffer with variable static distortions is proposed. These components are used to design a 64 TI-T&H sampling the signal at 60GS/s. Lastly, a calibration loop for a PAM-8 receiver that maximizes the linearity of the overall analog front-end by optimizing the bias voltage of the T&H is proposed. To validate the circuit a TSMC 5nm FinFET prototype has been designed while the linearity calibration loop and the other blocks of the PAM-8 receiver have been modeled in MATLAB and Verilog-A. The T&H circuit was co-simulated with the model, resulting in a T&H circuit with an output range of 505mVppd generated through a 6dB gain at Nyquist, a current consumption of 18.5mA from a 0.93V voltage supply, and over 48.5dB total harmonic distortion across different PVT conditions.