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Digital archive of theses discussed at the University of Pisa

 

Thesis etd-08012022-090135


Thesis type
Tesi di dottorato di ricerca
Author
PAGHI, ALESSANDRO
URN
etd-08012022-090135
Thesis title
Advanced Electrical Components and Sensors with Micro- and Nano- Materials
Academic discipline
ING-INF/01
Course of study
INGEGNERIA DELL'INFORMAZIONE
Supervisors
tutor Prof. Barillaro, Giuseppe
tutor Dott. Strambini, Lucanos Marsilio
Keywords
  • 3D capacitor
  • AgNPs
  • atomic layer deposition
  • capacitor
  • diode
  • nanocomposite
  • nanomaterial
  • PDMS
  • porous PDMS
  • porous silicon
  • pressure sensor
  • PSi
  • silver nanoparticles
Graduation session start date
05/05/2022
Availability
Withheld
Release date
05/05/2025
Summary
Semiconductors have become fundamental to twenty-first century society and have influenced human lives over the past 70 years. The passage from the past microelectronics era, where semiconductor devices had dimensions measured in micrometers (10^(-6) m), to the new nanoelectronics era, where the dimensions are shrunk down to nanometers (10^(-9) m), has made the semiconductor industry even more pervasive in our life. However, today the semiconductor industry cannot be exclusively focused on the same “business as usual” strategy, related to the fact that many aspects of the fabrication technology, design, and system level requirements are simultaneously changing approaching the fundamental limits at the nanoscale. The innovation at the nanoscale requires much more resources compared to the innovation performed in the past decades. In order to get around these limits, new materials and technology steps have been proposed in the recent years to increase the process variability, going insight the “More than Moore” era.
In chapter 2, I proposed the electrochemical micro-machining (ECM) of silicon for the fabrication of an array of 1 cm^2 surface, 2 um-diameter, 4 um-pitch, and 200 um-thick trenches in silicon as scaffold for a dielectric capacitor (DC). Then, atomic layer deposition (ALD) was used to conformally coat the inner surface of high AR trenches with a metal-insulator-metal stack, using TiN as metal, and both Al2O3 or HfAlOx as dielectrics, obtaining 3D DCs fully-integrated in silicon with areal capacitance up to 1 μF/mm^2, about 100 times higher than flat DCs counterpart. The proposed 3D DCs showed power and energy density of 566 W/cm^2 and 1.7 μWh/cm^2, respectively, with high-frequency operation (up to 70 kHz) and high-voltage bias (up to 16 V). These achievements open up perspective applications to on-chip energy storage for wearable and portable electronics. ECM can produce array of trenches with sub-micrometer diameter increasing the integration density and consequently the areal capacitance. Moreover, the bias voltage can be increased by improving the insulator quality by carefully tuning the ALD process parameters. Eventually, the frequency operation range can be increased lowering the series resistance of 3D DCs by reducing thickness and increasing doping level of the silicon wafer.
The electrochemical etching of silicon can be also scaled down to the nanoscale for the fabrication of nanostructured porous silicon (nPSi). Due to its morphology, nPSi shows peculiar properties (thermal, mechanical, optical, and electrical) when compared to bulk Si, opening new opportunities for silicon toward unexpected applications. Among electrical properties, mobility and lifetime of charge carriers in nPSi have been also reported to be tunable with respect to that of crystalline Si.
In chapter 3, I have demonstrated that leveraging the peculiar electrical properties of charge carriers when traveling in nanostructured porous silicon, namely, an extremely reduced mobility and lifetime, it is feasible to simultaneously improve the turn-off switching speed and the breakdown operation voltage of solid-state diodes integrated nearby. This is a key feature of the proposed nPSi technology, as two diverse technologies are usually required to separately adjust these parameters with other approaches. Specifically, peripheral integration of nPSi in n+–p diodes fabricated by an industrial process was shown to reliably increase the breakdown voltage by a factor >2× and to reduce the switching time by 30%, with respect to reference diodes without nPSi; no significant degradation of the other diode parameters was observed. The effect of nPSi was thoroughly assessed for different preparation conditions and diode architectures, demonstrating that the proposed approach was reliable and robust. The use of nPSi in microelectronics as a quasi-ideal mobility/lifetime sink for charge carriers opens up new opportunities for the design of advanced solid-state electrical components, such as signal and power transistors with improved performance and/or additional functionality. It also brings a number of advantages, with respect to traditional approaches used for carrier mobility and lifetime adjustment, including a smaller cost for material preparation and process integration, nPSi being prepared at room temperature by electrochemical transformation of crystalline Si; and, a higher integration density and scaling-down potential, thanks to the smaller integration pitch achievable for nPSi fabrication when carried out as an intermediate process step.
The high surface-to-volume ratio obtained with nPSi fabricated by electrochemical etching can be also useful to increase the effective area of DCs. Unfortunately, the high AR with nanometric diameter of pores represent a strong limitation in the conformal coating with standard thin film deposition techniques. Layer-by-layer (LbL) assembly is a pervasive diffused method for conformal surface coating of high AR substrates with nanometer and sub-nanometer-thick polyelectrolyte layers, which offers superior control and versatility with respect to other thin-film deposition methods, successfully employed for many different applications, as separation science, drug delivery, biomedicine, and biosensing.
In chapter 4, I leveraged the use of LbL nano-assembly technique to fabricate a nanometric-thick stacked polyelectrolytes capacitor (LbL capacitor) with electrostatically positive and negative charged polyelectrolytes, varying the number of LbL layers from 10 to 40. Impedance measurements versus frequency were recorded in order to extrapolate areal capacitance and phase angle, giving a maximum capacitance density value of 25 nF mm^-2 with a phase angle always lesser then -65° in the range 20 Hz - 1 MHz, indicating the strong capacitive behavior of the LbL stack, for all the number of bilayers investing in this work (from 10 to 40). The three different polarization mechanisms identified for bulk polyelectrolytes capacitors, i.e. dipolar relaxation at high frequencies, ionic relaxation at intermediate frequencies, and EDLs formation at the polymer/metal interfaces at low frequencies, were identified also for the sub-nanometric-thick polyelectrolyte layers stacked together. In addition, LbL capacitors present two different ionic relaxation processes, related to the EDLs formation by positive and negative ions near and far from the metal electrodes. This work opens new perspectives to the use of nanometric-thick polyelectrolytes in microelectronic for energy storage and gate insulating layers thanks to the ability of LbL technique to conformal coating high aspect ratio structure (>100).
Besides silicon, polymers provide an added value for the “More than Moore” era. Nanoparticle polymer composites have enabled material multifunctionalities that are difficult to achieve otherwise. The distinctive properties of the nanocomposites strongly depend on the collective organization of the hosted nanoparticles in the hosting material. Thus, controlling the size and distribution of nanoparticles on the hosting material is crucial to provide access to novel optical, electrical, and mechanical functionalities. Also in this case, this is even more challenging on 3D hosting materials, such as polymer foams, for which the conformal coating of the inner surface of the 3D pore network with NPs is further required.
In chapter 5, I focused my attention on the controlled and in-situ conformal coating of PDMS foams with AgNPs using a fluoride-rich chemistry, with surface coverage fine-tunable over a large range, namely, from 0 to 75%. The accurate control of the NP surface coverage enabled the design of AgNP electrical networks on the inner surface with tunable resistivity and optimized piezoresistive properties. I leveraged the control of the piezoresistive properties of the AgNP electrical network synthetized on the foam to fabricate flexible and wearable sensors with maximum sensitivity of 0.41 kPa^−1 and gauge factor of 12.46 for the detection of displacement of 4 um and pressure of 25 Pa, coupled with a large dynamic range up to 60% for strain (120 kPa for pressure) and high endurance over >1500 cycles of operation. The sensors were successfully used to monitor the real-time radial artery pulse wave on the human wrist of a young male with high resolution, from which I extracted typical parameters of clinical relevance. The proposed fluoride-rich method is room temperature, low cost, and highly reliable, and allow to coat 3D polymeric materials and networks with a conformal thin layer of metal NPs with controlled density and strong adhesion to the host material. The method can be immediately extended to other polymeric materials and metals, besides PDMS and Ag that were the subject of this study, to gain novel properties and applications of metal-polymer nanocomposites in wearable sensing, stretchable electronics, environment cleaning, and water remediation, among others.
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