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Digital archive of theses discussed at the University of Pisa


Thesis etd-07282022-145502

Thesis type
Tesi di dottorato di ricerca
Thesis title
Design of Mixed Signal CMOS cells for interfacing of next generation sensors
Academic discipline
Course of study
tutor Prof. Bruschi, Paolo
  • analog design
  • CMOS
  • custom interface
  • digital design
  • general purpose interface
  • integrated circuits
  • mixed signal design
  • sensor interfaces
  • system on chip
Graduation session start date
Release date
During the last years, a growing interest in collecting an as large as possible number of data from the environment, such as for air/water quality survey, security or healthcare purposes, has been noted. Typically, these applications are based on distributed sensor networks where every node is a stand-alone device capable
of performing the required measurements and transmitting the results to a common receiver. Thus, complex mixed-signal System-on-Chip (SoC) to interface these devices became of great interest. However, the increasing number of different sensors, that every device have to simultaneously measure, could require a wide number of dedicated interfaces, which means a high area and power demand. Thus, the number of sensors that a platform could manage strongly depends on the area and power application constraints. Anyway, this limitation could be solved designing compact general-purpose sensor interfaces capable of properly stimulating and sensing different kind of sensors. On the other hand, a large number of sensors, in particular novel, non standard, innovative and experimental devices, could require specifications non compatible with a general purpose approach. Thus, the design of both kinds of interface is currently adopted, based on the applications and the considered sensors.
The research activity presented in this thesis regards the design of these different sensor interface approaches, exploiting some external collaborations. The activity in which I was involved during all my PhD period was the development of the Sensiplus platform, a novel general-purpose sensor interface. For this platform I developed important Intellectual Properties (IPs) and I significantly improved the internal digital processing unit. In addition, I also started and partly completed the implementation of a companion chip (the Sensidrive) for the Sensiplus, aimed to allow the driving of several sensors/actuators that require voltages and currents higher than the Sensiplus capability. While for the Sensiplus the type of design was mainly low noise or digital processing automation, in this case the main design skills regarded high power and high voltage issues. Moreover, another stand-alone activity was the design of an interface for novel and advanced dual band optical sensors, developed by a research group I collaborated with. Even if the concept (it is not a general purpose approach) and the application are different, I could exploit part of the IPs (both analog and digital) implemented for the Sensiplus, but also the development of new specific cells was necessary. Finally, I had the opportunity, within the collaboration with a Marie Curie researcher, to work on an ultra low power interface for wearable applications.
To cope with the requirements aforementioned, since 2012 the Sensichips s.r.l., in partnership with the Department of Information Engineering of the University of Pisa, is developing a novel general-purpose sensor interface, the Sensiplus platform. This SoC (1.5mm x 1.5mm only) is capable of interfacing up to 8 external sensors and embeds some integrated sensors such as temperature, humidity and light sensors. It works with
a single supply voltage of 3.3V and down to 1.8V. The communication with this device can be performed by means of standard protocols (SPI, I2C) or with a single wire own protocol. It has also to be suitable for a wide number of measurements, including the Electrical Impedance Spectroscopy (EIS), in order to enable the reading of a large variety of sensors. Recently, new target applications with high voltage (up to 8 V) and high current (up to 300 mA) requirements have been addressed by the company. Since these requirements are incompatible with the Sensiplus (due to area and power limitations), a new interface called Sensidrive, in order to expand the Sensiplus functionalities, has been developed.
Photodetectors based on a Ge-on-Si platform were widely studied over the last two decades, rapidly becoming the technology of choice for CMOS-integrated optoelectronic systems operating in the near infrared. Recently, the research group of Prof. Lorenzo Colace (University of Roma Tre) demonstrated a proof-of-concept device realized (in collaboration with the Polytechnic of Milano) with a back-to-back, Ge-on-Si double photodiode with dual-band optical sensitivity and voltage-tunability characteristics. Such a device represents the cornerstone for the development of integrated imaging systems operating both in the Visible (VIS) and in the Near InfraRed (NIR) spectral ranges. Given the peculiar electronic behaviour of the proposed device, specific readout electronics must be developed and integrated onto a Complementary Metal-Oxide Semiconductor (CMOS) platform. Part of my research activity was focused on the design of this complete interface (Interphoto interface). The designed readout architecture can be easily scaled up to address a larger number of pixels (currently 32), thus showing the potentiality of the system for the development of an imaging device operating
in the VIS and NIR suitable for practical applications.
Internet-of-Wearable (IoW) is already a reality embodied in commercial products for fitness. These devices record activity data (speed, distance, heart-rate, impact forces) and are connected to the Cloud through Bluetooth enabled access points. Smart wearables of the next generation will integrate bio-chemical sensing to capture body dynamics at molecular level and in real time. Sweat, naturally produced by the human body, will enable non-invasive access to a rich sets of bio-markers. However, sweatbased IoW devices face many challenges: bio-compatibility, flexibility, durability, data integrity, low-power consumption, lightness in weight and low-cost fabrication. The SmartWearable for fatigue Tracking (SWeaT) project (funded by the European Union’s Horizon 2020 research and innovation programme) will address all these issues developing a low-cost wearable device capable of sensing and recording a full set of relevant electrolytes concentration in sweat, sweat rate and temperature. A custom SoC in low-cost CMOS technology to provide early readout and signal digitalization has been designed.