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Digital archive of theses discussed at the University of Pisa


Thesis etd-07072022-151037

Thesis type
Tesi di dottorato di ricerca
Thesis title
Addressing VLSI Design Challenges for High Data Rate Transmitters and Receivers in Satellite Applications
Academic discipline
Course of study
tutor Prof. Fanucci, Luca
  • digital design
  • high data-rate transmission
  • receivers
  • satellite applications
  • telemetry downlink
  • transmitters
Graduation session start date
Release date
Earth observation satellites are continuously evolving to match sensor technologies and digital processing advances. In particular, the growing concern about environmental problems related to global warming is driving the satellite industry towards monitoring the health of our planet. Consequently, all these factors also increase the demand for high-speed data transmissions, especially for the downlink of scientific telemetry data. This thesis provides a complete description of both transmitters and receivers for these kinds of Low Earth Orbit (LEO) applications. In particular, the analysis focuses on the Consultative Committee for Space Data Systems (CCSDS) 131.2-B-1 standard, which is one of the primary candidates for future missions planned by the European Space Agency (ESA). Therefore, this thesis investigates how this standard, and others related to it, can be effectively implemented in hardware to meet the throughput expected for future satellite missions. The work aims to explore the design space, from standards to physical implementations on Field Programmable Gate Array (FPGA) platforms. Concerning the transmitter side, the encoder design is remarkably detailed to address the parallel processing aspect and the congestion problems related to the physical placement of resources on the target platform. Architectures and their limitations are presented along with the optional or mandatory solutions to meet very-high throughput. Finally, the thesis describes a possible low-cost receiver architecture for low-medium data rates. This study includes the analysis of all synchronization algorithms and the related trade-off investigations to decide the proper architectures for the final proof-of-concept implementation. Along with all these considerations, the thesis details preliminary hardware end-to-end testing on a proof-of-concept prototype, where actual hardware data is taken from the test FPGAs and checked for consistency. To the best of the author's knowledge, this thesis represents the first in-depth and comprehensive analysis of the architectures and their trade-offs for the mentioned standards.