Tesi etd-07042016-164225 |
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Tipo di tesi
Tesi di laurea magistrale
Autore
IOZZELLI, YURI
URN
etd-07042016-164225
Titolo
Performance improvements on the P4 software switch
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
COMPUTER ENGINEERING
Relatori
relatore Prof. Rizzo, Luigi
relatore Prof. Lettieri, Giuseppe
relatore Prof. Lettieri, Giuseppe
Parole chiave
- SDN netmap optimization
Data inizio appello
22/07/2016
Consultabilità
Completa
Riassunto
The Programming Protocol-Independent Packet Processors (P4) is a
domain-specific language designed to allow programming of packet forwarding
dataplanes. It is used within a Software-Defined Networking (SDN) architecture,
and it is meant to replace the Openflow protocol, being more flexible and
powerful.
The reference software implementation of a P4 switch is currently used mainly
to test the correctness of P4 programs, before deploying them on hardware
switches. The software switch has poor performance in terms of throughput, and
this prevent it from being used in many different scenarios, like network
protocol experimentation and Virtual Machine interconnection.
The aim of this work is to analyze the bottlenecks of this implementation and
improve the performance, trying to reach a throughput with an order of
magnitude of 1 Mpps. Particular care has been used in making all the
modifications as compatible as possible with the existing code base, in order
to favour adoption of the improvements in existing and future applications.
domain-specific language designed to allow programming of packet forwarding
dataplanes. It is used within a Software-Defined Networking (SDN) architecture,
and it is meant to replace the Openflow protocol, being more flexible and
powerful.
The reference software implementation of a P4 switch is currently used mainly
to test the correctness of P4 programs, before deploying them on hardware
switches. The software switch has poor performance in terms of throughput, and
this prevent it from being used in many different scenarios, like network
protocol experimentation and Virtual Machine interconnection.
The aim of this work is to analyze the bottlenecks of this implementation and
improve the performance, trying to reach a throughput with an order of
magnitude of 1 Mpps. Particular care has been used in making all the
modifications as compatible as possible with the existing code base, in order
to favour adoption of the improvements in existing and future applications.
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