Tesi etd-07012023-192621 |
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Tipo di tesi
Tesi di laurea magistrale
Autore
RISTORI, LORENZO
URN
etd-07012023-192621
Titolo
Digital-twin design and experimental prototype validation of supercaps-based energy backup for automotive applications
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Prof. Saponara, Sergio
correlatore Dini, Pierpaolo
correlatore Dini, Pierpaolo
Parole chiave
- code validation
- digital twin
- processor-in-the-loop
- vehicle power electronics
Data inizio appello
21/07/2023
Consultabilità
Non consultabile
Data di rilascio
21/07/2093
Riassunto
The purpose of this project is to create a digital twin of a part of a schematic provided by MAGNA International, which concerns the energy backup system management of the e-latch. This system is designed to power the handle of an electric car in case the main power source, the battery, is depleted or malfunctions.
Specifically, the digital twin consists of: two 25F supercapacitors, a boost controller composed of an integrated circuit, a boost converter, and a microcontroller interface circuit consisting of MOSFETs and resistors.
Furthermore, the secondary objective of the project is to generate the code for managing the reading, charging, and discharging of the supercapacitors based on a state machine block diagram provided by MAGNA. This state machine is composed of a charge control part for the supercapacitors, a discharge part, a charge part, and other additional parts necessary for short circuit or open circuit control.
The following process steps were carried out: modeling the finite state machine using Stateflow in Simulink, verifying the various state machines that make up the main machine through tests using Simulink harness, verifying state coverage using Simulink test, verifying the model on the board using Processor-in-the-loop, generating C code for AUTOSAR and testing the code on the MAGNA dedicated board.
In the harness part, test sequence and assessment blocks were used to set inputs and verify that the outputs were consistent. In the coverage part, it was ensured that all branch conditions in the state machines were traversed and verified under both true and false conditions.
Through Processor-in-the-loop, the correct operation of the state machine on the NXP board, compatible with the microprocessor on the e-latch board, was verified. The PIL process verified the read, charge, and discharge conditions of the supercapacitors.
At the end of this process, the code was compared with the one provided by MAGNA technicians to ensure that it was more or less the same and potentially modifiable directly from the header files by the programmers.
Finally, the generated code was put on their microcontroller in their dedicated circuit and it was tested making some charging and discharging cycles to verify if it worked well also in an operative environment.
Specifically, the digital twin consists of: two 25F supercapacitors, a boost controller composed of an integrated circuit, a boost converter, and a microcontroller interface circuit consisting of MOSFETs and resistors.
Furthermore, the secondary objective of the project is to generate the code for managing the reading, charging, and discharging of the supercapacitors based on a state machine block diagram provided by MAGNA. This state machine is composed of a charge control part for the supercapacitors, a discharge part, a charge part, and other additional parts necessary for short circuit or open circuit control.
The following process steps were carried out: modeling the finite state machine using Stateflow in Simulink, verifying the various state machines that make up the main machine through tests using Simulink harness, verifying state coverage using Simulink test, verifying the model on the board using Processor-in-the-loop, generating C code for AUTOSAR and testing the code on the MAGNA dedicated board.
In the harness part, test sequence and assessment blocks were used to set inputs and verify that the outputs were consistent. In the coverage part, it was ensured that all branch conditions in the state machines were traversed and verified under both true and false conditions.
Through Processor-in-the-loop, the correct operation of the state machine on the NXP board, compatible with the microprocessor on the e-latch board, was verified. The PIL process verified the read, charge, and discharge conditions of the supercapacitors.
At the end of this process, the code was compared with the one provided by MAGNA technicians to ensure that it was more or less the same and potentially modifiable directly from the header files by the programmers.
Finally, the generated code was put on their microcontroller in their dedicated circuit and it was tested making some charging and discharging cycles to verify if it worked well also in an operative environment.
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