• coarse-grained reconfigurable architectures
• graph attention networks
• graph neural networks
• processing element
• reconfigurable computing
• standard cell
• tile
• verification environment

In recent years, reconfigurable computing has become very popular in a wide scope of applications. Among all available architectures, Coarse-Grained Reconfigurable Arrays appear to be some of the most interesting ones, as they permit to efficiently accelerate several classes of data-intensive algorithms without giving up architecture versatility. Unfortunately, their use in the most advanced Graph Neural Networks is not well investigated. In this work, the most relevant Coarse-Grained Reconfigurable Array devices and Graph Neural Network models are analyzed and possible architectural implications of Graph Neural Network inference in hardware are discussed. The main contribute of the thesis is given by the design and characterisation of the Processing Element of a novel Coarse-Grained Reconfigurable Architecture optimised for the execution of Graph Neural Networks. The architecture tile, which is entirely configurable, has been integrated within a user-defined UVM verification environment and validated by means of randomization. Utilization and timing results for its implementation on a Field Programmable Gate Array are derived, as well as area, timing and power results for standard cell synthesis on a TSMC 40 nm low power technology. The latter shows favorable results in terms of area and power consumption and returns a maximum working frequency in line with values reported by other state-of-the-art works that deal with Coarse-Grained Reconfigurable Architectures.