• memoria associativa
• sequencer
• Silicon Vertex Trigger
• SVT

This thesis has the following structure:
• In the chapter 1 the CDF experiment is introduced and the role of the SVT device is
explained. Each board that is part of the SVT device is highlighted and its architecture is explained focalizing the attention on the AMS-RW, AM++ with its plug-in LAMB++ boards, object of my thesis. Moreover a short introduction of the Boundary Scan tools is reported.
• In the chapter 2 I describe all the work that concerns the diagnostic of the two boards. In particular is explained the development of the test tools to globally check and simulate the data taking and check the connections of all the boards. Moreover I describe my work to include diagnostic tools inside the logic architecture of the chips placed on the AM++ and LAMB++.
• In the chapter 3 the Pulsar board is introduced and its architecture is described. It is shown how it is possible to use the Pulsar to realize the AMS-RW. The chapter reports all the work on the VHDL firmware. Moreover the internal test tool of the SVT (Spy Buffers and Error Flags) development is described.
• In the Appendix A the details of the program used in the thesis are reported.
• In the Appendix B the Boundary Description language and its use in my thesis is described.