• ldpc
• encoder
• design
• implementation
• configurability
• dvb-s2
• throughput
• fpga
• vhdl

This Master's Thesis, the result of my experience with the Department of Information (DII) at the University of Pisa and with Ingeniars S.r.l, focuses on designing and implementing an LDPC (Low Density Parity Check) Encoder on a Xilinx FPGA. The encoder will be utilized as part of the a DVB-S2 Transmitter IP for a High Data-Rate Downlink Telemetry System in the context of the Earth Exploration Satellite Service, with specific focus on achieving the following characteristics:
- High Throughput: The design will prioritize maximizing data processing speed to ensure efficient transmission and reception of the payload.
- Full Compliance with DVB-S2 Standard: The encoder will be designed to comply with the DVB-S2 Standard for all possible data rates. This will enable the utilization of Adaptive Coding and Modulation (ACM) and Variable Coding and Modulation (VCM) techniques, optimizing transmission efficiency by adapting to varying channel conditions.
- Highly Reconfigurable I/O Interfaces: The input and output interfaces of the LDPC Encoder will be designed for high reconfigurability, which will allow easy adaptation to different operational requirements and facilitate seamless integration into diverse systems.
- AXI Stream Pipelined Architecture: The LDPC Encoder will employ an AXI Stream pipelined architecture. This architecture choice will enhance data transfer efficiency between different functional blocks within the FPGA design, minimizing latency and maximizing overall system performance.