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Tesi etd-06132013-222642


Thesis type
Tesi di laurea magistrale
Author
CARNEVALE, BERARDINO
URN
etd-06132013-222642
Title
Implementation of Augmented Reality applications on Reduced Instruction Set Computers: characterization, profiling and possible architecture improvements
Struttura
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Commissione
correlatore Ing. Davalle, Daniele
relatore Prof. Fanucci, Luca
Parole chiave
  • Application Specific Instruction Set Computers
  • Augmented Reality
  • Application Profiling
  • LISA Language
  • Reduced Instruction Set Computers
Data inizio appello
19/07/2013;
Consultabilità
parziale
Data di rilascio
19/07/2053
Riassunto analitico
The target of this project is to profile and propose hardware modifications for Marker based Augmented Reality (AR) applications, when implemented on Application Specific Reduced Instruction Set Computer (RISC). <br>The tasks have been performed during an internship at RWTH Aachen University, Institute for Communications Technologies and Embedded Systems. <br>The test case is a C++ application implemented on the top of ARToolKitPlus, an open source C++ library. The main steps of a Marker-based AR application are analyzed, pointing out the computationally intensive kernels when executed on a Personal Computer. <br>The application has also been profiled on two different kinds of processor simulators: the ARM Cortex A9 virtual platform and the RISC (PDRISC) given by Synopsys with the tool Processor Designer. The profiling has been implemented modifying the scripts, the LISA (Language for Instruction Set Applications) and C++ models for both processors. The profiling tools have been organized to be automated and reproduced after further modifications. The results of profiling show that in a Marker based AR applications the computationally intensive kernels on RISCs are the image labeling algorithm, the camera error compensation function and some complementary interests algorithms. <br>Considering that, some possible architecture improvements to speed up this kernels are also given. The most important are: the parallel computation of labeling algorithm, the addition of a Floating Point Unit and the framework to perform matrix operations using one reduced instruction.
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