ETD system

Electronic theses and dissertations repository

 

Tesi etd-06072017-234029


Thesis type
Tesi di laurea magistrale
Author
CELIA, MARCO EMANUELE
URN
etd-06072017-234029
Title
From natural language requirements to Simulation Monitors: Synthesis through code generation
Struttura
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
EMBEDDED COMPUTING SYSTEMS
Commissione
relatore Prof. Di Natale, Marco
correlatore Prof. Buttazzo, Giorgio C.
Parole chiave
  • Model Based Design
  • Requirements
  • Code Generation
  • Embedded
Data inizio appello
24/07/2017;
Consultabilità
completa
Riassunto analitico
The increasing level of complexity of modern embedded systems concurs to enhance the gap between the textual representation of High-Level System Requirements and the testing units in charge of their verification. Such gap is worsened by the possible presence of errors and omissions in the natural language requirement and causes engineers to inject into the verification units features derived from their personal interpretation.<br> <br>This work has the goal to provide a framework consisting of a requirements (loose) syntax, a requirements editor, a parser, and an automatic synthesis tool, which helps engineers in writing high-level requirements in a structured natural language with a contract-based paradigm, thus reducing, as much as possible, inconsistency and common errors, and directly generating verification monitors for a target platform.<br> <br>To restrict the domain and the framework complexity and make the problem affordable, the first version of the tool is restricted to the controls domain and assumes the use of Simulink as a modeling and simulation tool. To ease the generation process, a control verification Simulink library has been implemented.
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