• riscv
• hardware accelerator
• fpga
• floating-point
• posits

The IEEE 754 Standard for floating-point arithmetic has been for decades implemented in the vast majority of modern computer systems to manipulate real numbers.
Recently, John L. Gustafson introduced a new datatype called posit to represent real numbers on computers, with the promise of sunsetting the IEEE 754 standard by delivering more accurate results, higher dynamic range, improved accuracy, and more.

The objective of this thesis work is to design a posit-arithmetic core-generator, i.e., a hardware-software framework able to generate a hardware description language (HDL) file of a posit processing unit (PPU) accelerator, suitable as a drop-in replacement for existing floating-point units (FPU) aboard CPUs.

To that end, a preliminary software library was developed and thoroughly tested to model the design space and create a conducive environment.

The generated posit processing units have been synthesized into a smattering of reconfigurable hardware devices to gauge performance responses over a set of FPGA families, and their results are discussed and compared to similar works available in the literature.

Moreover, a pipelined version of said posit arithmetic core generator has been spawned and amended, exhibiting superior performance in terms of both frequency rate and overall latency.

Lastly, extensions of the base RISC-V instruction set architecture (ISA) have been defined and tested to enable direct access to the posit processing unit core by a host RISC-V CPU.